限制穩壓器啟動(dòng)時(shí)dV/dt和電容的電路

有時(shí)，設計約束突出地暴露了平凡器件和電路的不利方面。這種案例有供電源穩壓電路的設計，電路中一次電源有完全限流規定，例如太空船的光電或“日光”板和放射性同位元素熱電發(fā)生器。這種應用需要謹慎嚴格的控制電流消耗，包括瞬變電流消耗和罕見(jiàn)消耗尖峰，例如那些上電時(shí)典型發(fā)生的。問(wèn)題是限流一次電源即使響應瞬間的過(guò)流故障，都會(huì )損害災難性的電壓降并關(guān)閉。通常這種故障由穩壓器輸出的去耦電容釋放的電流尖峰引起。

除非穩壓器限流削弱發(fā)生的尖峰，尖峰與穩壓器輸出電壓上升速率與并聯(lián)輸出總電容的乘積相等：I_MAX=dV/dt×C_OUT，其中I_MAX是最大電流，dV/dt為電壓對時(shí)間的微分，C_OUT為輸出電容。公式表明限制穩壓器接通最大電流的最佳策略是限制dV/dt。如圖1電路基于這個(gè)方法，使用工業(yè)標準的可調線(xiàn)性穩壓器，例如流行的low-dropout LM2941。

限制dV/dt方法的基礎包含6個(gè)額外器件：R₃、R₄、C_T、D₁、D₂和Q₁。上電時(shí)，控制電流通過(guò)R₃、C_T和D₂使輸出電壓上升延遲，因此阻止了過(guò)大的瞬時(shí)最大電流。

下面是其工作過(guò)程。當VI_N打開(kāi)且Q₁關(guān)閉時(shí)，電流通過(guò)R₃、C_T和D₂上拉穩壓器參考端到參考電壓。這個(gè)動(dòng)作限制了V_OUT 的dV/dt到C_T通過(guò)串聯(lián)電阻放電的速率，(R₃+R₁R₂/(R₁+R₂))，使用公式R₃=(VI_N–V_REF–1)/V_OUT，R₄=20R₃,和C_T=C_OUTV_OUT/(I_MAX(R₃+R₁R₂/(R₁+R₂)))，從而限制I_MAX到任何需要值。例如，假定電路如圖所示，C_OUT=100 μF，dV/dt=2500V/s，且I_MAX=0.25A。在改進(jìn)的上電序列后部，D₁和D₂從穩壓器反饋網(wǎng)絡(luò )中分離dV/dt電路，防止從輸入到輸出紋波電壓的耦合。

英文原文：

Circuit limits dV/dt and capacitor inrush at regulator turn-on

Adding a simple circuit to the adjust pin of a regulator controls the dV/dt of the output voltage, limiting inrush current.

W Stephen Woodward, Chapel Hill, NC; Edited by Charles H Small and Fran Granville -- EDN, 10/11/2007

Unusual design constraints sometimes reveal the unfriendly side of everyday components and circuits. A case in point is the design of power-supply-regulation circuitry in which the primary power source has an absolute current-limit specification, such as spacecraft photovoltaic, or “solar,” panels and radioisotope-thermoelectric generators. Such applications require that you pay scrupulous attention to strict control of current consumption, including transient-current consumption, and infrequent consumption spikes, such as those that typically occur on power-up. The problem is that current-limited primary-power sources can suffer catastrophic voltage droop and shutdown in response to momentary overcurrent faults, even when the fault is brief. Common causes of such faults are the current spikes that charge the regulator output’s decoupling capacitor.

Unless the current limit of the regulator clips the resulting spikes, the spikes are equal to the regulator’s output-voltage rate of rise multiplied by the sum of the parallel output capacitances: IMAX="dV/dt"×COUT, where IMAX is the maximum current, dV/dt is a differential in voltage with respect to a differential in time, and COUT is the output capacitance. The math suggests that the best strategy for limiting the regulator’s turn-on maximum current is to limit dV/dt. The circuit in Figure 1 relies on this trick and works with industry-standard adjustable linear regulators, such as the popular low-dropout LM2941.

The basis of the dV/dt-limiting technique comprises the six added components: R3, R4, CT, D1, D2, and Q1. On power-up, the control current through R3, CT, and D2 delays the rise of the output voltage and thus prevents excessive maximum-current transients.

Here’s how it works. When VIN is on and Q1 is off, current through R3, CT, and D2 pulls the adjust pin of the regulator to the reference. This action limits VOUT’s dV/dt to the rate of CT charging through the series resistance, (R3+R1R2/(R1+R2)), and thereby limits IMAX to any desired value using the design equations R3=(VIN–VREF–1)/VOUT, R4=20 R3, and CT="COUTVOUT/"(IMAX(R3+R1R2/(R1+R2))). For example, given the circuit constants in the figure and assuming COUT="100" μF, dV/dt=2500V/s, and IMAX="0".25A. At the end of the modified power-up sequence, D1 and D2 decouple the dV/dt circuit from the regulator’s feedback network, preventing the coupling of ripple voltages from the input voltage into the output voltage.

英文原文地址：http://www.edn.com/article/CA6486029.html