U-boot1.1.6移植到TQ2440開(kāi)發(fā)板(上)

if(bBootFrmNORFlash())

{

pdwDest = (unsignedint*)buf;

pdwSrc = (unsignedint*)start_addr;

for(i = 0; i < size / 4; i++)

{

pdwDest[i] = pdwSrc[i];

}

return0;

}

else

{

nand_init_ll();

if(NF_ReadID() == 0x76 )

{

nand_read_ll(buf, start_addr, (size + NAND_BLOCK_MASK)&~(NAND_BLOCK_MASK));}

else

{

nand_read_ll_lp(buf, start_addr, (size + NAND_BLOCK_MASK_LP)&~(NAND_BLOCK_MASK_LP));}

return0;

}

}

staticinlinevoiddelay(unsignedlongloops)

{

__asm__volatile("1:n"

"subs %0, %1, #1n"

"bne1b":"=r"(loops):"0"(loops));

}

#defineS3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01)) //HJ 400MHz

#defineS3C2440_MPLL_405MHZ ((0x7f<<12)|(0x02<<4)|(0x01)) //HJ 405MHz

#defineS3C2440_MPLL_440MHZ ((0x66<<12)|(0x01<<4)|(0x01)) //HJ 440MHz

#defineS3C2440_MPLL_480MHZ ((0x98<<12)|(0x02<<4)|(0x01)) //HJ 480MHz

#defineS3C2440_MPLL_200MHZ ((0x5c<<12)|(0x01<<4)|(0x02))

#defineS3C2440_MPLL_100MHZ ((0x5c<<12)|(0x01<<4)|(0x03))

#defineS3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02)) //HJ 100MHz

#defineS3C2440_CLKDIV 0x05 //HJ 100MHz

#defineS3C2440_CLKDIV136 0x07 //HJ 133MHz

#defineS3C2440_CLKDIV188 0x04

#defineS3C2440_CAMDIVN188 ((0<<8)|(1<<9))

#defineS3C2440_MPLL_399MHz ((0x6e<<12)|(0x03<<4)|(0x01))

#defineS3C2440_UPLL_48MHZ_Fin16MHz ((60<<12)|(4<<4)|(2))

voidclock_init(void)

{

S3C24X0_CLOCK_POWER*clk_power = (S3C24X0_CLOCK_POWER*)0x4C000000;

#ifCONFIG_133MHZ_SDRAM

clk_power->CLKDIVN = S3C2440_CLKDIV136; //HJ 1:3:6

#else

clk_power->CLKDIVN= S3C2440_CLKDIV; //HJ 1:4:8

#endif

__asm__( "mrc p15, 0, r1, c1, c0, 0n"

"orr r1, r1, #0xc0000000n"

"mcr p15, 0, r1, c1, c0, 0n"

:::"r1"

);

clk_power->LOCKTIME= 0xFFFFFF;

clk_power->UPLLCON= S3C2440_UPLL_48MHZ; //fin=12.000MHz

// clk_power->UPLLCON = S3C2440_UPLL_48MHZ_Fin16MHz; //fin=16.934MHz

delay (4000);

clk_power->MPLLCON= S3C2440_MPLL_400MHZ; //fin=12.000MHz

// clk_power->MPLLCON = S3C2440_MPLL_405MHZ; //HJ 405MHz

// clk_power->MPLLCON = S3C2440_MPLL_440MHZ; //HJ 440MHz

// clk_power->MPLLCON = S3C2440_MPLL_480MHZ; //HJ 480MHz

// clk_power->MPLLCON = S3C2440_MPLL_399MHz; //fin=16.934MHz

delay (8000);

}

修改cpu/arm920t/s3c24x0/speed.c中g(shù)et_HCLK等函數,首先在前面添加DECLARE_GLOBAL_DATA_PTR;使其能使用gd_t全局數據結構的指針

FLCK、HCLK和PCLK的關(guān)系

S3C2440有三個(gè)時(shí)鐘FLCK、HCLK和PCLK

FCLK is used by ARM920T，內核時(shí)鐘，主頻。

HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and USB host block. 也就是總線(xiàn)時(shí)鐘，包括USB時(shí)鐘。

PCLK is used for APB bus, which is used by the peripherals such as WDT, IIS, I2C, PWM timer, MMC interface,ADC, UART, GPIO, RTC and SPI.即IO接口時(shí)鐘，例如串口的時(shí)鐘設置就是從PCLK來(lái)的；

具體代碼：

staticulongget_PLLCLK(intpllreg)

{

S3C24X0_CLOCK_POWER* constclk_power = S3C24X0_GetBase_CLOCK_POWER();

ulongr, m, p, s;

if(pllreg == MPLL)

r = clk_power->MPLLCON;

elseif(pllreg == UPLL)

r = clk_power->UPLLCON;

else

hang();

m = ((r & 0xFF000) >> 12) + 8;

p = ((r & 0x003F0) >> 4) + 2;

s = r & 0x3;

if(gd->bd->bi_arch_number== MACH_TYPE_SMDK2410)

return((CONFIG_SYS_CLK_FREQ * m) / (p << s));

else

return((CONFIG_SYS_CLK_FREQ * m *2) / (p << s));

}

ulongget_FCLK(void)

{

return(get_PLLCLK(MPLL));

}

#defineS3C2440_CLKDIVN_PDIVN (1<<0)

#defineS3C2440_CLKDIVN_HDIVN_MASK (3<<1)

#defineS3C2440_CLKDIVN_HDIVN_1 (0<<1)

#defineS3C2440_CLKDIVN_HDIVN_2 (1<<1)

#defineS3C2440_CLKDIVN_HDIVN_4_8 (2<<1)

#defineS3C2440_CLKDIVN_HDIVN_3_6 (3<<1)

#defineS3C2440_CLKDIVN_UCLK (1<<3)

#defineS3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)

#defineS3C2440_CAMDIVN_CAMCLK_SEL (1<<4)

#defineS3C2440_CAMDIVN_HCLK3_HALF (1<<8)

#defineS3C2440_CAMDIVN_HCLK4_HALF (1<<9)

#defineS3C2440_CAMDIVN_DVSEN (1<<12)

ulongget_HCLK(void)

{

S3C24X0_CLOCK_POWER* constclk_power = S3C24X0_GetBase_CLOCK_POWER();

unsignedlongclkdiv;

unsignedlongcamdiv;

inthdiv = 1;

clkdiv = clk_power->CLKDIVN;

camdiv = clk_power->CAMDIVN;

if(gd->bd->bi_arch_number== MACH_TYPE_SMDK2410)

return((clk_power->CLKDIVN& 0x2) ? get_FCLK()/2 : get_FCLK());

else

{

switch(clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {

caseS3C2440_CLKDIVN_HDIVN_1:

hdiv = 1;

break;

caseS3C2440_CLKDIVN_HDIVN_2:

hdiv = 2;

break;

caseS3C2440_CLKDIVN_HDIVN_4_8:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;

break;

caseS3C2440_CLKDIVN_HDIVN_3_6:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;

break;

}

returnget_FCLK() / hdiv;

}

}

ulongget_PCLK(void)

{

S3C24X0_CLOCK_POWER* constclk_power = S3C24X0_GetBase_CLOCK_POWER();

unsignedlongclkdiv;

unsignedlongcamdiv;

inthdiv = 1;

clkdiv = clk_power->CLKDIVN;

camdiv = clk_power->CAMDIVN;

if(gd->bd->bi_arch_number== MACH_TYPE_SMDK2410)

return((clk_power->CLKDIVN& 0x1) ? get_HCLK()/2 : get_HCLK());

else

{

switch(clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {

caseS3C2440_CLKDIVN_HDIVN_1:

hdiv = 1;

break;

caseS3C2440_CLKDIVN_HDIVN_2:

hdiv = 2;

break;

caseS3C2440_CLKDIVN_HDIVN_4_8:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;

break;

caseS3C2440_CLKDIVN_HDIVN_3_6:

hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;

break;

}

returnget_FCLK() / hdiv / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);

}

}