LOGi FPGA 開(kāi)發(fā)板：可在樹(shù)莓派和Beaglebone上開(kāi)發(fā)FPGA

最近在Kickstarter網(wǎng)站上，Valent F(x)團隊正在為L(cháng)OGi FPGA開(kāi)發(fā)板的生產(chǎn)籌備資金。

LOGi 是fpga開(kāi)發(fā)與arm平臺的結合。Valent F(x)團隊開(kāi)發(fā)了可以支持樹(shù)莓派和Beaglebone上開(kāi)發(fā)的FPGA開(kāi)發(fā)板，LOGi系列。它讓FPGA開(kāi)發(fā)與入門(mén)變得簡(jiǎn)單，同時(shí)趨于統一現存硬件接口和開(kāi)源開(kāi)發(fā)平臺，如樹(shù)莓派和Beaglebone Black這兩個(gè)流行的開(kāi)源開(kāi)發(fā)平臺。

Valent F(x)團隊分別針對樹(shù)莓派和Beaglebone Black開(kāi)發(fā)了兩個(gè)版本的LOGi板，如下圖的LOGi-Pi和LOGi-Bone。LOGi-Pi的FPGA板的底部連接器可與樹(shù)莓派的GPIO頭連接，LOGi-Bone的FPGA板有兩行的連接器可與Beaglebone Black 2x46引腳頭相連接。不需要JTAG或者繁雜的命令，只需要在樹(shù)莓派或者Beaglebone Black平臺的終端輸入logi_loader.bit，就可以運行LOGi板。

LOGi-Pi for the Raspberry Pi

LOGi-Pi 的基本技術(shù)參數:

Xilinx Spartan 6 LX9 FPGA 9,152 Logic Cells, 16 DSP48A1 Slices, 576Kb RAM

Plug-and-Play Interfacing for the Raspberry Pi 4 Layer Optimized Design to Support Maximum Performance of High Bandwidth Applications Length-tuned GPMC, SDRAM, LVDS Signals

3.3V I/O Regulator and 1.2V Core Regulator

256 Mb SDRAM connected to the FPGA

2x LEDs 2x Push Buttons 2x DIP Switches

1x High Bandwidth SATA connector expansion, port Length tuned and impedance routed differential signals for maximum bandwidth (Designed for modular LVDS expansion, Not SATA devices - see FAQ on SATA connector)

2x Digilent Inc. PMOD ports supporting 59+ plug-and-play hardware modules

1x Arduino compatible headers connected to the FPGA pins (3.3V only) Supports over 200+ Arduino Shield Modules

10x Length-tuned LVDS Pairs 32 FPGA I/O available through PMOD and Arduino headers

Connection to the SPI Interface of the Raspberry Pi (3.8 MBps maximum Bandwidth)

Connection to 16 I/O of the Raspberry Pi expansion port (including SPI, UART, I2C and GCLK and GPIO).

Bit-Stream loading interface connected to the host processor, optional bitstream FPGA self-loading from onboard Flash.

LOGi-Bone for the Beaglebone

LOGi-Bone的基本技術(shù)參數:

Xilinx Spartan 6 LX9 TQFP-144 FPGA 9,152 Logic Cells, 16 DSP48A1 Slices, 576Kb RAM

Beaglebone Black Optimized 4 Layer Optimized Design to Support Maximum Performance of High Bandwidth Applications Length-tuned GPMC, SDRAM, LVDS Signals 3.3v I/O Regulator and 1.2v Core

Regulator 256 Mb SDRAM connected to the FPGA

2x LEDs 2x Push Buttons 2x DIP Switches

1x High Bandwidth SATA connector expansion port, Length tuned and impedance routed differential signals for maximum bandwidth (Designed for modular LVDS expansion, Not SATA devices - see FAQ on SATA connector)

2x Digilent Inc. PMOD ports supporting 59+ plug-and-play hardware modules

1x Arduino compatible headers connected to the FPGA pins (3.3V only) Supports over 200+ Arduino Shield Modules

Optional GPMC, SPI or I2C port access from the Beaglebone Black

10x Length-tuned LVDS Pairs

Bit-Stream loading interface connected to the host processor, optional bitstream FPGA self-loading from onboard Flash.