基于FPGA的UART、USB接口協(xié)議設計
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//clk_bps sync bps generater
reg clk_bps_r0,clk_bps_r1,clk_bps_r2;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
clk_bps_r0 = 0;
clk_bps_r1 = 0;
clk_bps_r2 = 0;
end
else
begin
if(bps_cnt1 32'h7FFF_FFFF)
clk_bps_r0 = 0;
else
clk_bps_r0 = 1;
clk_bps_r1 = clk_bps_r0;
clk_bps_r2 = clk_bps_r1;
end
end
assign clk_bps = ~clk_bps_r2 clk_bps_r1;
//------------------------------------------
//clk_smp sync receive bps generator
reg clk_smp_r0,clk_smp_r1,clk_smp_r2;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
clk_smp_r0 = 0;
clk_smp_r1 = 0;
clk_smp_r2 = 0;
end
else
begin
if(bps_cnt2 32'h7FFF_FFFF)
clk_smp_r0 = 0;
else
clk_smp_r0 = 1;
clk_smp_r1 = clk_smp_r0;
clk_smp_r2 = clk_smp_r1;
end
end
assign clk_smp = ~clk_smp_r2 clk_smp_r1;
endmodule
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