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EEPW首頁(yè) > 嵌入式系統 > 設計應用 > 關(guān)于A(yíng)RM9協(xié)處理器CP15及MCR和MRC指令

關(guān)于A(yíng)RM9協(xié)處理器CP15及MCR和MRC指令

作者: 時(shí)間:2016-11-24 來(lái)源:網(wǎng)絡(luò ) 收藏

本文引用地址:http://dyxdggzs.com/article/201611/320982.htm

寄存器1:Control register

對該寄存器讀寫(xiě)指令如下:

MRCp15, 0, Rd, c1, c0, 0; read control register

MCRp15, 0, Rd, c1, c0, 0; write control register

該寄存器功能如下表

Registe bits

Name

Function

Value

31

iA bit

Asynchronous clock select

見(jiàn)時(shí)鐘模式表

30

nF bit

notFastBus select

見(jiàn)時(shí)鐘模式表

29:15

-

Reserved

Read = Unpredictable

Write = should be zero

14

RR bit

Round robin replacement

0 = Random replacement

1 = Round robin replacement

13

V bit

Base location of exception register(異常寄存器基地址)

0 = Low address = 0x0000 0000

1 = High address = 0xFFFF 0000

12

I bit

Instruction cache enable

0 = Instruction cache disable

1 = Instruction cache enable

11:10

-

Reserved

Read = 00

Write = 00

9

Rbit

ROM protection

見(jiàn)圖1

8

Sbit

System protection

見(jiàn)圖1

7

Bbit

Big-endian/little-endian

0 = Little-endian operation

1 = Big-endian operation

6:3

-

Reserved

Read = 1111

Write = 1111

2

C bit

Data cache enable

0 = data cache disable

1 = data cache enable

1

A bit

Alignment fault enable

Data address alignment fault checking

(地址對齊檢查)

0 =禁用地址對齊檢查功能

1 =使能地址對齊檢查功能

0

M bit

MMU enable

0 = MMU disable

1 = MMU enable

時(shí)鐘模式表

Clocking mode(時(shí)鐘模式)

iA

nF

Fastbus mode (快速總線(xiàn)模式)

0

0

Reserved

1

0

Synchronous (同步模式)

0

1

Asynchronous (異步模式)

1

1

圖1

寄存器2:Translation Table Base(TTB) Register

Register bits

Function

31:14

Pointer to first level translation table base . Read /write

13:0

Reserved

Read = Unpredictable

Write = Should be zero

訪(fǎng)問(wèn)C2寄存器指令如下:

MRC p15, 0, Rd, C2, C0, 0 ; Read TTB register

MCR p15, 0, Rd, C2, C0, 0 ; Write TTB register

該寄存器存放第一級轉換表基地址。寫(xiě)入時(shí),位[13:0]必須為0,讀出時(shí),位[13:0]的值不可預知。

寄存器3:Domain Access Control Register

寄存器3是可讀寫(xiě)的域訪(fǎng)問(wèn)控制寄存器,分為16組,每組占用2個(gè)位

訪(fǎng)問(wèn)該寄存器的指令如下:

MRCp15, 0, Rd, C3, C0, 0;Read domain 15:0 access permissions

MCRp15, 0, Rd, C3, C0, 0;Read domain 15:0 access permissions

Interpreting Access Control Bits in Domain Access Control Register

寄存器4:保留

對該寄存器的讀寫(xiě)會(huì )產(chǎn)生不可預料的結果。

寄存器5:Fault Status Register

寄存器6:Fault Address Register

寄存器7:Cache Operations

該寄存器是只寫(xiě)寄存器,用于管理指令緩存和數據緩存。

對該寄存器的寫(xiě)操作所實(shí)現的功能,是通過(guò)MCR指令中的opcode_2和CRm兩者的組合來(lái)選擇的,具體組合如下。

寄存器8:TLB Operations

Register 8 is a write-only register used to manage the translation lookaside buffer(TLBs),the instruction TLB and the data TLB.

Five TLB operations are defined and the function to be performed is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8.Writing other opcode_2 or CRm values id unpredictable. Reading from CP15 register 8 is unpredictable.

FunctionDatainstruction
Invalidate TLB(s)SBZMCR p15,0,Rd,c8,c7,0
Invalidate I TLBSBZMCR p15,0,Rd,c8,c5,0
Invalidate I TLB single entry (using MVA)MVA formatMCR p15,0,Rd,c8,c5,1
Invalidate D TLBSBZMCR p15,0,Rd,c8,c6,0
Invalidate D TLB single entry (using MVA)MVA formatMCR p15,0,Rd,c8,c6,1


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關(guān)鍵詞: ARM9協(xié)處理器CP15MRC指

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